1. Field of the Invention
The present invention relates to a method of testing a memory module and a hub of memory module.
2. Description of the Related Art
The increase of speed and/or circuit integration of main memory may correlate with the enhancement of operating speeds of central processing circuits. A bus architecture, which may perform at high speeds for packet transmitting and/or receiving between the central processing circuit and the main memory, may be used to augment data input and/or data output speeds of the main memory. Further, a memory module having a plurality of memory chips mounted on a printed circuit board (PCB) may be used to augment a memory capacity of the main memory.
The memory module may be classified as single In-line memory module (SIMM) a dual In-line memory module (DIMM). A SIMM may be a memory module having memory chips mounted only on one side of the PCB, whereas, a DIMM may be a memory module having memory chips mounted on both sides of the PCB.
There may be several options for increasing the memory capacity of main memory. Using memory modules may increase memory capacity. Also, increasing memory clock frequencies may enhance memory data access rates, which may cause data transfer rates to change, leading to increased memory capacity. Additionally, the number of memory chips mounted on the memory module and/or the number of slots of motherboard may be increased to provide more memory capacity.
Unfortunately, as a clock frequency of memory is increased, a timing margin of the memory may decrease. Also, if the number of slots of motherboard is increased, then signal transmission of a transmission line may be weakened by generation of load impedance. Registered DIMM, a type of DIMM, may be used to compensate for these signal transmission weaknesses.
FIGS. 1A and 1B illustrate block diagrams showing a conventional registered DIMM and buffered DIMM, respectively.
Referring to FIG. 1A, a registered DIMM may have a phase locked loop (PLL) 103, register 101, and a plurality of memories 105.
When a registered DIMM is mounted on a motherboard, the registered DIMM may compensate for the generation of load impedance. When the motherboard has many slots and/or the clock frequency is high, a reflected wave may be generated, degrading the transmission efficiency. To overcome the degradation of the transmission efficiency, buffered DIMM may be used. The buffered DIMM may have a hub for receiving packets and transforming the packets into a memory command.
Referring to FIG. 1B, a buffered DIMM may have a hub 107 and a plurality of memories 109. The hub 107 may receive packets and provide the packets to the plurality of memories 109 mounted on the memory module with a memory command and data. Furthermore, the hub 107 may packetize data outputted from the memory to supply data to a memory controller in packet form.
FIG. 2A is block diagram that illustrates a testing method of a conventional memory module.
Referring to FIG. 2A, the testing method may use a plurality of memory modules 220-1, 220-2, . . . , 220-N and a bus structure suitable for transmission of a packet from one memory module to other memory modules. Furthermore, the bus structure may be positioned between a hub 222 and/or a memory controller 210 for suitable transmission of the packet. A channel of Point-to-Point (P2P) type may be formed between the memory controller 210 and each respective memory module 220-N and then signals may be transferred between the memory controller 210 and the memory modules 220-1, 220-2, . . . , 220-N in a daisy chain manner. Therefore, the load impedance of the transmission lines may be reduced.
The packet, which may be received from the memory controller 210, may have an identification code indicative of memory module destination. When the identification code of the received packet matches a particular memory module 220-i, the hub of the particular memory module 220-i may process the received packet and/or may transmit the data to the corresponding memory 224.
Two methods may be used when testing a memory module using automatic test equipment. The first method of testing may be Built-In Self Test (BIST). This method may include preparing testing logic in the hub to test the memory when a specific mode selection signal is applied to the memory module. However, when using BIST, degradation of test coverage due to testing the memory with a fixed test pattern may occur.
The second method of testing may be using a transparent mode. In the transparent mode test, a control signal may be applied to a memory module and signals may be inputted from automatic test equipment. These signals may then be directly inputted into memory. However, since the signals from the test equipment are directly inputted to the memory, a difference may be present between a tab number in the memory module and a tab number required for testing the memory module. Further, when a data comparison is performed in the hub, the data inputted to the memory may be stored in a register. Using a register to perform the data comparison may require a complex circuit and/or may raise difficulty in synchronizing the compared data.
FIG. 2B is a table comparing a tab number of the buffered DIMM with a tab number required for testing the buffered DIMM in a transparent mode.
In a normal mode, signals inputted and outputted from/to the buffered DIMM are all differential signals. A term “northbound” in the table of FIG. 2B indicates a packet that is outputted from the memory controller 210 to be inputted to the buffered DIMM, and a term “southbound” indicates a packet that is outputted from the buffered DIMM to be inputted to the memory controller 210. In addition, a term “primary” indicates a packet inputted to the hub 222 and a term “secondary” indicates a packet outputted from the hub 222.
Referring to FIG. 28, a buffered DIMM in the normal mode may have 14 tabs or pins for a primary northbound (PN) packet, 14 tabs or pins for a complementary primary northbound (/PN), 10 tabs or pins for a primary southbound (PS), 10 tabs or pins for a complementary primary southbound (/PS), 14 tabs or pins for a secondary northbound (SN), 14 tabs or pins for a complementary secondary northbound (/SN), 10 tabs or pins for a secondary southbound (SS) and 10 tabs or pins for a complementary secondary southbound (/SS). For example, the buffered DIMM may have total 96 tabs or pins. However, to test the memory in the transparent mode, several tabs or pins, for example, 8 tabs or pins may be required for memory control signals such as /CS, /RAS, /CAS, /WE, etc. Further, several tabs or pins, for example, 18 tabs or pins may be required for address signals, several tabs or pins, for example, 72 tabs or pins may be required for data (DQ) signals, and several tabs or pins, for example, 18 tabs or pins may be required for data strobe signals (DQS). For example, more tabs or pins are required than the memory module has. In the above example, at least 116 tabs or pins may be required to test the memory in the transparent mode and therefore, in the transparent mode, the memory module may not have enough tabs or pins.